Column redundancy circuit and memory device including same

A column redundancy circuit of a memory device, the column redundancy circuit comprising:

• a first pre-decoder configured to
• receive a lower column address from a plurality of fault column addresses, and
• perform a OneHot (OH) decoding operation;
• a second pre-decoder configured to
• receive an upper column address from the plurality of fault column addresses, and
• perform a Binary to Thermometer Code (BTC) decoding operation;
• a main decoder configured to
• receive a lower signal from the first pre-decoder,
• receive an upper signal from the second pre-decoder, and
• perform a main decoding operation;
• a shift logic configured to generate a shift signal that enables a column shift operation based on a result of the main decoding operation;
• and
• a multiplexer configured to
• receive the shift signal, and
• perform the column shift operation based on selecting a bit line of a plurality of bit lines.

A memory device comprising:

• a memory cell array including a redundancy cell array and a normal cell array;
• and
• a column redundancy circuit connected to the memory cell array through a plurality of bit lines, the column redundancy circuit configured to control access to a memory cell of the redundancy cell array through a column shift operation based on a defect occurring in a memory cell of the normal cell array,
• wherein the column redundancy circuit includes,
• a pre-decoder circuit configured to
• receive a lower column address from a plurality of fault column addresses,
• perform a first decoding operation,
• receive an upper column address from the plurality of fault column addresses, and
• perform a second decoding operation;
• a main decoder circuit including a plurality of main decoders, each main decoder of the plurality of main decoders configured to
• receive a lower signal and an upper signal from the pre-decoder circuit, and
• perform a main decoding operation;
• and
• a shift logic circuit including a plurality of shift logics, each shift logic of the plurality of shift logics configured to generate a shift signal that enables the column shift operation based on a result of the main decoding operation.