US 12,580,583 B2 · Differential successive approximation register analog-to-digital converter with dynamic input common-mode voltage control and associated method

Abstract

A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.

Claims14

Dependent claims

A differential successive approximation register (SAR) analog-to-digital converter (ADC), comprising:

a comparator circuit, having a non-inverting input terminal and an inverting input terminal;
a sampling circuit, arranged to sample a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC;
a first capacitive digital-to-analog converter (DAC), coupled to the non-inverting input terminal of the comparator circuit;
a second capacitive DAC, coupled to the inverting input terminal of the comparator circuit;
a SAR logic circuit, arranged to control the first capacitive DAC and the second capacitive DAC during a SAR phase of the differential SAR ADC;
and
a common-mode voltage control circuit, arranged to dynamically adjust an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has a first voltage level during the sample phase and a second voltage level during the SAR phase, and the second voltage level is different from the first voltage level.

4 more elements

A differential successive approximation register (SAR) analog-to-digital conversion method, comprising:

during a sample phase of a differential SAR analog-to-digital conversion operation,
sampling a differential voltage input to generate and output a differential comparator input to a comparator circuit, wherein the comparator circuit has a non-inverting input terminal and an inverting input terminal;
and
setting an input common-mode voltage of the comparator circuit by a first voltage level;
and
during a SAR phase of the differential SAR analog-to-digital conversion operation,
controlling a first capacitive digital-to-analog converter (DAC) that is coupled to the non-inverting input terminal of the comparator circuit and a second capacitive DAC that is coupled to the inverting input terminal of the comparator circuit;
and
adjusting the input common-mode voltage of the comparator circuit to have a second voltage level, wherein the second voltage level is different from the first voltage level.

6 more elements

Dependencies are inferred from the claim text.

Differential successive approximation register analog-to-digital converter with dynamic input common-mode voltage control and associated method

Life of this patent

Differential successive approximation register analog-to-digital converter with dynamic input common-mode voltage control and associated method

Life of this patent

Abstract

Claims14