Low parasitic capacitance architecture for successive approximation register analog-to-digital converters

A capacitor array comprising:

• a plurality of unit capacitors, wherein each respective unit capacitor further comprises:
• a first capacitor, wherein the first capacitor comprises:
• a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction;
• a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction, and an integral shielding structure disposed at least partially under at least part of the first plate;
• wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers;
• and
• a second capacitor coupled to the first, wherein the second capacitor includes at least part of one of the first plate or second plate.

A system comprising:

• a circuit configured to sample and generate an input signal;
• a digital-to-analog converter configured to receive the input signal from the circuit and generate an output signal based, at least in part, on the input signal, wherein the digital-to-analog converter further comprises:
• a capacitor array, wherein the capacitor array comprises a plurality of unit capacitors, wherein each respective unit capacitor further comprises:
• a first capacitor, wherein the first capacitor comprises:
• a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction;
• and
• a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction, and an integral shielding structure disposed at least partially under at least part of the first plate;
• wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers;
• and
• a second capacitor coupled to the first, wherein the second capacitor includes at least part of one of the first plate or second plate;
• and
• a comparator configured to compare the output signal to a reference voltage;
• and
• logic configured to generate a digital code based, at least in part, on an output of the comparator.