Phase aligning multiple channel dividers without stopping VCO root clock

A system, comprising:

• clock channels on a clock chip, each clock channel configured to provide a clock signal;
• a tri-statable signal line coupled to the clock channels, the tri-statable signal line configured to transport clock signals;
• a controller configured to select a first clock signal from a first clock channel to transport on the tri-statable signal line;
• and
• divider timing synchronization circuitry in a second clock channel configured to align a second clock signal from the second clock channel with the first clock signal.

A method, comprising:

• selecting a first clock channel in a clock chip, wherein the clock chip includes a plurality of clock channels;
• transmitting a first clock signal from the first clock channel on a signal line coupled to each of the plurality of clock channels;
• receiving the first clock signal at a second clock channel;
• and
• aligning a second clock signal from the second clock channel with the first clock signal wherein aligning the second clock signal includes determining a phase error between the first clock signal and the second clock signal.

An apparatus comprising:

• a root clock generator having an output;
• a signal line;
• and
• a first clock channel including:
• first channel clock generator circuitry having a clock input coupled to the output of the root clock generator and having a clock output coupled to the signal line;
• and
• alignment circuitry having an alignment error indicator output, and a time-to-digital converter (TDC) having first and second clock inputs, the first clock input of the TDC coupled to the signal line, the second clock input of the TDC coupled to the clock output of the first channel clock generator circuitry;
• and
• a second clock channel including second channel clock generator circuitry having a clock input coupled to the output of the root clock generator and having a clock output coupled to the signal line.