Methods and apparatus to protect transistors using voltage clamp circuitry

An apparatus comprising:

• a first transistor having a first terminal, a second terminal, and a control terminal;
• first clamp circuitry having a first terminal and a second terminal, the first terminal of the first clamp circuitry coupled to the control terminal of the first transistor;
• second clamp circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the second clamp circuitry coupled to the first terminal of the first transistor, the second terminal of the second clamp circuitry coupled to the control terminal of the first transistor;
• and
• clamp control circuitry including:
• a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the third terminal of the second clamp circuitry;
• a comparator having an input and an output, the input of the comparator coupled to the second terminal of the second transistor;
• and
• a logic gate including an input and an output, the input of the logic gate coupled to the output of the comparator, the output of the logic gate coupled to the second terminal of the first clamp circuitry.

A system comprising:

• a transistor having a first terminal, a second terminal, and a control terminal;
• first clamp circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the first clamp circuitry coupled to the control terminal of the transistor, the second terminal of the first clamp circuitry coupled to the first terminal of the transistor;
• second clamp circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the second clamp circuitry coupled to the second terminal of the transistor, the second terminal of the second clamp circuitry coupled to the control terminal of the transistor;
• safe operating area (SOA) circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the SOA circuitry coupled to the second terminal of the transistor, the second terminal of the SOA circuitry coupled to the control terminal of the transistor, the SOA circuitry configured to enable the first clamp circuitry responsive to a drain-to-source voltage of the transistor;
• and
• clamp control circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the clamp control circuitry coupled to the control terminal of the transistor, the second terminal of the clamp control circuitry coupled to the third terminal of the first clamp circuitry, the third terminal of the clamp control circuitry coupled to the third terminal of the second clamp circuitry, the fourth terminal of the clamp control circuitry coupled to the third terminal of the SOA circuitry.