Voting-based state selection for a volatile memory

Abstract

An apparatus includes vote aggregation circuitry configured to receive a first plurality of vote signals associated with an active memory state of a volatile memory and to generate a first vote aggregation signal based on the first plurality of vote signals. The vote aggregation circuitry is further configured to receive a second plurality of vote signals associated with a retention memory state of the volatile memory and to generate a second vote aggregation signal based on the second plurality of vote signals. The apparatus further includes memory bank control circuitry coupled to the vote aggregation circuitry and configured to provide a plurality of control signals to the volatile memory based on the first vote aggregation signal and the second vote aggregation signal. The plurality of control signals indicate, for each bank of a plurality of banks of the volatile memory, a mode associated with the bank.

Dependencies are inferred from the claim text.