Apparatuses and methods for forcing memory cell failures in a memory device

An apparatus, comprising:

• a plurality of row latch sets, each row latch set of the plurality of row latch sets corresponding to a respective one of a plurality of redundant rows of memory, each row latch set of the plurality of row latch sets configured to store a respective row repair address, and when an incoming row address matches the respective stored row repair address, to provide a respective row match signal;
• a row disable control circuit coupled to the plurality of row latch sets to receive the respective row match signals, the row disable control circuit configured to provide an active row disable match signal when a designated one of the plurality of row latch sets provides an active row match signal and the disable memory test mode is enabled;
• a plurality of column latch sets, each column latch set of the plurality of column latch sets corresponding to a respective one of a plurality of redundant columns of memory, each column latch set of the plurality of column latch sets configured to store a respective column repair address and associated column plane address, and when an incoming column address matches the respective stored column repair address, to provide a respective column match signal and the associated column plane address;
• and
• a column disable control circuit coupled to the plurality of column latch sets to receive the respective column match signals and the associated column plane addresses, the column disable control circuit configured to provide a redundant column select signal that is inactive and an active column plane masking signal corresponding to an active match signal of a designated column latch set of the plurality of column latch sets when a disable memory test mode is enabled to cause a memory of main memory to fail.

A method, comprising:

• comparing an incoming column address to a column address and associated plane address stored in a designated column latch set;
• activating a match signal provided by the designated column latch set when the incoming column address matches the column address stored in a designated column latch set;
• and
• providing from a column disable control circuit an active redundant column select signal and an active column plane masking signal responsive to the active match signal and a disable memory test mode is not enabled, and providing from the column disable control circuit an inactive redundant column select signal and the active column plane masking signal responsive to the active match signal and a disable memory test mode is enabled to force memory cells of a main memory array to fail.