Semi-polling input/output completion mode for non-volatile memory express completion queue

A computer system comprising:

• a processor system;
• and
• a computer storage medium that stores computer-executable instructions that are executable by the processor system to at least:
• receive, by an interrupt thread, an input/output (I/O) request from an application;
• submit, by the interrupt thread, a submission queue (SQ) entry into a Non-Volatile Memory Express (NVMe) SQ in response to the I/O request;
• register, by the interrupt thread, for notifications from a polling thread after submitting the SQ entry, including registering for a software interrupt from the polling thread;
• responsive to the registering, identifying, by the polling thread, whether an NVMe completion queue (CQ) entry that corresponds to the SQ entry is present within an NVMe CQ without removing the CQ entry from the NVMe CQ;
• receive, by the interrupt thread, the software interrupt from the polling thread, the software interrupt signaling a presence of a completion queue (CQ) entry within an NVMe CQ, including receiving the software interrupt from the polling thread;
• remove, by the interrupt thread, the CQ entry from the NVMe CQ in response to receiving the software interrupt;
• and
• notify, by the interrupt thread, the application of completion of the I/O request.

A computer-readable hardware storage medium that stores computer-executable instructions that are executable by a processor system to implement at an interrupt thread that is configured to at least:

• receive, by the interrupt thread, an input/output (I/O) request from an application;
• submit, by the interrupt thread, a submission queue (SQ) entry into a Non-Volatile Memory Express (NVMe) SQ in response to the I/O request;
• register, by the interrupt thread, for notifications from a polling thread after submitting the SQ entry;
• responsive to the registering, identify, by the polling thread, whether an NVMe completion queue (CQ) entry that corresponds to the SQ entry is present within an NVMe CQ without removing the CQ entry from the NVMe CQ;
• receive, by the interrupt thread, a software interrupt from the polling thread, the software interrupt signaling a presence of the CQ entry within the NVMe CQ;
• remove, by the interrupt thread, the CQ entry from the NVMe CQ in response to receiving the software interrupt;
• and
• notify, by the interrupt thread, the application of completion of the I/O request.