Processor and method of detecting soft error from processor

A method of detecting a soft error, the method comprising:

• executing an original instruction in an instruction pipeline of a processor;
• storing an execution result of the original instruction in a register of nth index of an original register file of the processor;
• duplicating the original instruction as a duplicate instruction;
• executing the duplicate instruction in the instruction pipeline;
• storing an execution result of the duplicate instruction in a register of an nth index of a duplicate register file of the processor;
• comparing a first value of the register of the nth index of the original register file with a second value of the register of the nth index of the duplicate register file;
• and
• based on the comparison between the first value and the second value, outputting an error detection signal indicative of a presence of a soft error in execution of the original instruction.

A processor comprising at least two cores, wherein each of the at least two cores comprises:

• an instruction pipeline comprising a plurality of stages, wherein the instruction pipeline is configured to process an original instruction in the plurality of stages in a first instruction cycle, and to process a duplicate instruction in the plurality of stages in a second instruction cycle immediately following the first instruction cycle;
• an original register file comprising a plurality of registers, wherein the instruction pipeline is configured to temporarily store an execution result of the original instruction in the original register file;
• an original program counter, wherein the processor is configured to change a value of the original program counter in the first instruction cycle and to maintain the value of the original program counter in the second instruction cycle;
• a duplicate register file comprising a same number of registers as the original register file, wherein the instruction pipeline is configured to temporarily store an execution result of the duplicate instruction in the duplicate register file;
• a duplicate program counter, wherein the processor is configured to change a value of the duplicate program counter in the second instruction cycle and to maintain the value of the duplicate program counter in a third instruction cycle immediately following the second instruction cycle;
• and
• a comparing unit configured to compare values of registers of a same index in (i) the original register file and the duplicate register file or (ii) the original program counter and the duplicate program counter, and to, based on the comparison, output an error detection signal indicative of a presence of a soft error in execution of the original instruction.