Biased indirect control transfer prediction
AssigneeApple Inc.
InventorsMuawya M Al-Otoom, Pruthivi Vuyyuru, Andrew H Lin, Ian D Kountanis
Life of this patent
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Abstract
A processor may include an indirect control transfer prediction circuit. During fetch of an indirect control transfer instruction from memory to an instruction cache of the processor, the indirect control transfer prediction circuit may predict whether the indirect control transfer instruction is biased. Responsive to a prediction that the indirect control transfer instruction is biased, the indirect control transfer prediction circuit may cause the indirect control transfer instruction to be executed as an unconditional direct control transfer instruction according to the predicted bias.
Claims20
A processor, comprising:
- a prefetch circuit configured to prefetch instructions including an indirect control transfer instruction from memory to an instruction cache;
- and
- a prediction circuit configured to perform, during prefetch of the indirect control transfer instruction to the instruction cache:
- predict whether the indirect control transfer instruction is biased;
- and
- direct, responsive to a prediction that the indirect control transfer instruction is biased, the prefetch circuit to store a predicted target address in the instruction cache to cause the indirect control transfer instruction to be executed, subsequent to fetching from the instruction cache, as an unconditional direct control transfer instruction according to the predicted bias.
A system, comprising:
- one or more processors individually comprising an instruction cache;
- memory configured to store instructions;
- and
- a display configured to display images;
- wherein the one or more processors individually comprise:
- a prefetch circuit configured to prefetch instructions including an indirect control transfer instruction from memory to an instruction cache;
- and
- a prediction circuit configured to perform, during prefetch of the indirect control transfer instruction to the instruction cache:
- predict whether the indirect control transfer instruction is biased;
- and
- responsive to a prediction that the indirect control transfer instruction is biased, direct the prefetch circuit to store a predicted target address in the instruction cache to cause the indirect control transfer instruction to be executed, subsequent to fetching from the instruction cache, as, an unconditional direct control transfer instruction according to the predicted bias.
A method, comprising:
- prefetching instructions, including an indirect control transfer instruction, by a prefetch circuit of a processor from memory to an instruction cache;
- performing, during prefetching of the indirect control transfer instruction to the instruction cache, by a bias prediction circuit of the processor:
- predicting whether the indirect control transfer instruction is biased;
- and
- responsive to a prediction that the indirect control transfer instruction is biased, directing the prefetch circuit to store a predicted target address in the instruction cache to cause execution, by the processor subsequent to fetching from the instruction cache, of the indirect control transfer instruction as an unconditional direct control transfer instruction according to the predicted bias.
Dependencies are inferred from the claim text.