Interface circuit and memory controller

A memory controller, coupled to a memory device to control access operations of the memory device, comprising:

• a host interface, configured to communicate with a host device and comprising a signal processing circuit to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
• a plurality of signal processing devices;
• and
• a monitor and calibration module, comprising:
• a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency, and a jitter in at least one of the reception signal and the transmission signal to generate a first monitored result corresponding to the at least one of the amplitude, the frequency, and the jitter in the at least one of the reception signal and the transmission signal and to monitor at least one of a power supplying voltage and a ground voltage to generate a second monitored result corresponding to the at least one of the power supplying voltage and the ground voltage in a monitor and calibration procedure;
• a plurality of calibration circuits, coupled to the plurality of signal processing devices and respectively configured to perform a calibration operation on at least one of the plurality of signal processing devices in the monitor and calibration procedure to adjust a characteristic value of the at least one of the plurality of signal processing devices;
• and
• a compensation control mechanism operation logic, coupled to the plurality of monitor circuits and the plurality of calibration circuits and configured to collect the first monitored result and the second monitored result from the plurality of monitor circuits and sequentially generate a calibration control signal corresponding to each calibration circuit based on the first monitored result and the second monitored result to respectively control the corresponding calibration circuit to perform the calibration operation on the at least one of the plurality of signal processing devices in response to the calibration control signal,
• wherein the compensation control mechanism operation logic is implemented by a Field Programmable Gate Array (FPGA) and comprises:
• a calibration handle interface, coupled to the plurality of calibration circuits and configured to receive and decode a calibration command and generate the calibration control signal according to a decoding result of the calibration command, and transmit the calibration control signal to at least one of the plurality of calibration circuits.