Scan chain control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJia Han Lin, Shih-Chang Tsai, Feng-Ming Kuo, Chung-Sheng Yuan, Chung-Hsing Wang, Yi-Kan Cheng
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.
Claims20
A control circuit for loading a repeated sequence to a plurality of flip flops, the control circuit comprising:
- a bit counter configured to receive as input a first control signal, a second control signal, and a scan clock signal, the bit counter further configured to output a first bit and a second bit based on the first control signal, the second control signal, and the scan clock signal;
- a multiplexer configured to receive the first bit and the second bit as input and output a sequence of bits;
- a first group control circuit configured to receive the sequence of bits as input and output a first group control signal;
- and
- a second group control circuit configured to receive the sequence of bits as input and output a second group control signal.
A scan chain circuit, comprising:
- a plurality of flip flops, the plurality of flip flops including single bit flip flops and multi-bit flip flops and are in a predetermined output to input sequence;
- and
- a control circuit comprising:
- a bit counter configured to receive as input a first control signal, a second control signal, and a scan clock signal, the bit counter further configured to output a first bit and a second bit;
- one or more multiplexers configured to receive the first bit and the second bit as input and output a sequence of bits;
- one or more first group control circuits configured to receive the sequence of bits as input and output a first group control signal to one or more corresponding multi-bit flip flops;
- and
- one or more second group control circuits configured to receive the sequence of bits as input and output a second group control signal to the one or more corresponding multi-bit flip flops.
A method for testing a plurality of flip flops, comprising:
- providing a plurality of flip flops, wherein the plurality of flip flops includes one or more single bit flip flops and one or more multi-bit flip flops, the one or more single bit flip flops and the one or more multi-bit flip flops in a predetermined output to input sequence;
- determining a number of accumulated bits from each flip flop to a scan chain output;
- categorizing each flip flop of the plurality of flip flops into a plurality of groups based on one or more rules, wherein a first rule of the one or more rules is based on the number of accumulated bits;
- providing a control circuit including a plurality of outputs corresponding to the plurality of groups, wherein the control circuit includes a first input signal port and a second input signal port;
- outputting, by the control circuit, a predetermined repeated sequence of bits into the plurality of flip flops;
- and
- determining a scan chain diagnosis based on an output from the plurality of flip flops.
Dependencies are inferred from the claim text.