US 12,578,379 B2 · Unified measurement system for static and dynamic characterization of a device under test

Abstract

A test and measurement system includes a device under test (DUT) interface structured to couple to first and second DUTs that are coupled to form a half bridge circuit. A characterization circuit is controlled to perform static testing and dynamic testing of the first and second DUTs. The characterization circuit includes a solid-state bias tee including the first DUT and a first drive voltage generator that provides a DC pulse signal and AC signal on a gate node of the first DUT to cause the first DUT to supply current and voltage signals to the second DUT for static and dynamic characterization of the second DUT. One characterization circuit can generate, at the same time, the gate charge characterization parameters for one DUT and reverse current path (e.g., body diode) characterization of another DUT.

Claims20

Dependent claims

A test and measurement system, comprising:

a device under test (DUT) interface structured to couple to first and second DUTs that are coupled to form a half bridge circuit;
and
a characterization circuit structured to be controlled to perform static testing and dynamic testing of the first and second DUTs, the characterization circuit including:
a solid-state bias tee including:
the first DUT;
and
a first drive voltage generator to provide a DC pulse signal and AC signal on a gate node of the first DUT to cause the first DUT to supply current and voltage signals to the second DUT for static and dynamic characterization of the second DUT.

4 more elements

A test and measurement system, comprising:

a device under test (DUT) interface structured to couple to top and bottom field-effect transistors (FETs) that are coupled to form a half bridge circuit, each FET including a reverse current path;
and
a characterization circuit structured to be controlled to perform gate charge curve testing of the top and bottom FETs, the characterization circuit including:
a test inductor coupled between a switching node of the half bridge circuit and a voltage node;
and
top and bottom gate drive circuits configured to supply respective gate drive signals to gates of the top and bottom FETs, the top or bottom gate drive circuit configured to turn ON the one of the top and bottom FETs being characterized until a current through the inductor reaches a threshold value and to thereafter turn OFF the one of the top and bottom FETs being characterized, and the gate drive circuit of the one of the top and bottom FETs being characterized configured to then provide a constant current to the gate of the one of the top and bottom FETs being characterized and the characterization circuit configured to measure the voltage on the gate of the one of the top and bottom FETs being characterized to measure gate charge characteristics.

3 more elements

A test and measurement system, comprising:

a device under test (DUT) interface structured to couple to top and bottom field-effect transistors (FETs) that are coupled to form a half bridge circuit, each FET including a reverse current path;
and
a characterization circuit structured to be controlled to perform reverse current path characterization of the top and bottom FETs, the characterization circuit including:
a test inductor coupled between a switching node of the half bridge circuit and a voltage node;
and
top and bottom gate drive circuits configured to supply respective gate drive signals to gates of the top and bottom FETs, the bottom or top gate drive circuit configured to turn ON one of the top and bottom FETs until a current through the inductor reaches a threshold value and to thereafter turn OFF the one of the FETs that was turned ON, the turning OFF causing the inductor current to flow through the reverse current path of the other FET being characterized, the characterization circuit configured to measure voltage and current parameters of the FET being characterized to determine reverse current path characteristics of the FET being characterized.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/626,190Filed 3 Apr 2024 · continuation in part

Priority

15 Mar 2021

Published

US 2024/0248131 A125 Jul 2024

Granted

17 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/2601
Testing of individual semiconductor devices: apparatus or methods therefor
G01R 31/2837
Fault-finding or characterising: characterising or performance testing, e.g. of frequency response
G01R 31/2621
Circuits therefor: for testing field effect transistors, i.e. FET's
G01R 31/2844
Fault-finding or characterising: using test interfaces, e.g. adapters, test boxes, switches, PIN drivers

Family

Application63/161,382Us provisional application · filed 15 Mar 2021

Application63/260,513Us provisional application · filed 23 Aug 2021

Application17/688,733Parent of this continuation-in-part · filed 7 Mar 2022

Application63/458,075Us provisional application · filed 7 Apr 2023

Application63/464,143Us provisional application · filed 4 May 2023

Application63/523,836Us provisional application · filed 28 Jun 2023

US 2024/0248131 A1Pre-grant publication · published 25 Jul 2024

US 12,498,414 B2Related patent

US 2022/0291278 A1Published application

US 12,578,379 B2This patent

From the US filing history. Foreign family members aren’t listed.

Unified measurement system for static and dynamic characterization of a device under test

Life of this patent

Unified measurement system for static and dynamic characterization of a device under test

Life of this patent

Abstract

Claims20