Test devices and systems that utilize efficient test algorithms to evaluate devices under test

A method of testing a memory device, comprising:

• supplying an input voltage through a power voltage pin to the memory device;
• transmitting a clock signal to the memory device;
• transmitting a command signal to the memory device;
• measuring, using a current sensor, a first current flowing through the power voltage pin to the memory device, in a first period of the clock signal subsequent to transmission of the command signal;
• then
• measuring, using the current sensor, a second current flowing through the power voltage pin to the memory device, in a second period of the clock signal subsequent to the first period of the clock signal and
• determining whether the memory device has a defect based on the first current and the second current.

A test system, comprising:

• a device under test (DUT) including a semiconductor memory device having a core circuit therein;
• and
• a test device configured to:
• (i) supply an input voltage to the DUT, (ii) generate a command signal that causes the DUT to perform a first operation using first circuitry within the core circuit within the DUT, and a second operation using second circuitry within the core circuit within the DUT, (iii) transmit the command signal to the memory device, (iv) measure, using a current sensor, a current flowing to the DUT as a first current when performing the first operation, (v) measure, using the current sensor, a current flowing to the DUT as a second current when performing the second operation, and (vi) determine whether the DUT is operating to satisfy a normal timing parameter based on the first current and the second current;
• and
• wherein the first circuitry is not identical to the second circuitry.