Systems and methods for seizure detection

An apparatus to detect seizures comprising:

• a feature detection circuit configured to detect a plurality of features associated with one or more electroencephalogram (EEG) signals;
• a bitstream generator configured to generate a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities;
• and
• feature evaluation circuitry configured to generate a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features, the feature evaluation circuitry including:
• a set of p-channel metal-oxide semiconductor (PMOS) transistors coupled in series between a voltage rail and a common node, wherein a gate of each of the set of PMOS transistors are configured to receive a respective one of the plurality of bitstreams,
• a set of n-channel metal-oxide semiconductor (NMOS) transistors coupled in series between the common node and a reference potential node, wherein a gate of each of the set of NMOS transistors are configured to receive the respective one of the plurality of bitstreams, and
• a latch comprising a pair of inverters coupled between the common node and an output of the feature evaluation circuitry.

A seizure detection system comprising:

• one or more electrodes configured to generate one or more electroencephalogram (EEG) signals;
• an amplification circuit configured to amplify the one or more EEG signals to yield one or more amplified EEG signals;
• a feature detection circuit configured to detect a plurality of features associated with each of the one or more amplified EEG signals;
• a bitstream generator configured to generate a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities;
• and
• feature evaluation circuitry configured to generate a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features, the feature evaluation circuitry including:
• one or more p-channel metal-oxide semiconductor (PMOS) transistors coupled in series between a voltage rail and a common node, wherein a gate of the one or more PMOS transistors is configured to receive at least one of the plurality of bitstreams,
• one or more n-channel metal-oxide semiconductor (NMOS) transistors coupled in series between the common node and a reference potential node, wherein a gate of the one or more NMOS transistors is configured to receive the at least one of the plurality of bitstreams, and
• a latch comprising one or more inverters coupled between the common node and an output of the feature evaluation circuitry.