US 12,575,394 B2Granted

Three-dimensional integrated circuit with top chip including local interconnect for body-source coupling

AssigneeGlobalFoundries U.S. Inc.

InventorsAnupam Dutta, Satyasuresh VVss Choppalli, Rui Tze Toh

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Abstract

Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.

Claims20

Dependent claims

A structure comprising:

a first chip;
and
a second chip, wherein the first chip is stacked on the second chip and includes:
first dielectric material layers adjacent to the second chip;
a first insulator layer;
a first transistor including a first active device region stacked vertically between the first dielectric material layers and the first insulator layer,
wherein, within the first active device region, the first transistor includes:
a first source region;
a first drain region;
a first channel region;
and a first body region on the first channel region,
wherein the first channel region and the first body region are positioned laterally between the first source region and the first drain region, and wherein the first transistor further includes a first gate structure within the first dielectric material layers immediately adjacent to a surface of the first active device region at the first channel region;
and
a local interconnect within the first insulator layer immediately adjacent to another surface of the first active device region opposite the first gate structure, wherein the local interconnect electrically couples the first body region and the first source region.

11 more elements

A structure comprising:

a first chip;
and
a second chip, wherein the first chip is stacked on the second chip and includes:
first dielectric material layers adjacent to the second chip;
a first insulator layer;
a first transistor including a first active device region stacked vertically between the first dielectric material layers and the first insulator layer,
wherein, within the first active device region, the first transistor includes:
first drain regions;
a first source region;
first channel regions;
and first body regions on the first channel regions, respectively,
wherein each first channel region and corresponding first body region on the first channel region are positioned laterally between the first source region and one of the first drain regions, and
wherein the first transistor further includes first gate structures within the first dielectric material layers immediately adjacent to a surface of the first active device region at the first channel regions, respectively;
and
a local interconnect within the first insulator layer immediately adjacent to another surface of the first active device region opposite the first gate structure, wherein the local interconnect electrically couples the first source region and the first body regions.

12 more elements

A method comprising:

forming a first chip;
forming a second chip;
stacking the first chip on the second chip, wherein the first chip includes:
first dielectric material layers adjacent to the second chip;
a first insulator layer;
and
a first transistor between the first dielectric material layers and the first insulator layer, wherein the first transistor includes:
a first source region;
a first drain region;
a first channel region;
a first body region on the first channel region, wherein the first channel region and the first body region are positioned laterally between the first source region and the first drain region;
and a first gate structure between the first channel region and the first dielectric material layers;
forming a trench that extends through the first insulator layer to the first source region and the first body region;
and
forming a local interconnect within the trench immediately adjacent to the first source region and the first body region.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/340,220Filed 23 Jun 2023
Published: US 2024/0429128 A126 Dec 2024
Granted: 10 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10D 30/711
Insulated-gate field-effect transistors [IGFET]: having floating bodies
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes