FET with multi-value switching function

A field effect transistor (FET) with a multi-value switching function comprising a main structure, a gate dielectric layer and a substrate layer, wherein the main structure comprises a source region, a channel region and a drain region which are distributed on the substrate layer from left to right and connected in sequence, the source region is made from NiAl alloy, the channel region is an undoped channel region and is made from an InAs material, the drain region is an undoped drain region and is made from an InAlAs material, and the gate dielectric layer is stacked on the source region and extends to the top of the channel region,

• wherein the FET further comprises:
• a gate-oxide inducer layer stacked on the drain region and extends to the top of the channel region to be connected to the gate dielectric layer;
• a metal layer comprising a first metal block, a second metal block and a third metal block which are arranged at intervals from left to right, wherein the first metal block is stacked on the gate dielectric layer, the second metal block is stacked on the gate-oxide inducer layer, and the third metal block is stacked on the gate-oxide inducer layer, and wherein the distance between the first metal block and the second metal block is 12 nm, and the distance between the second metal block and the third metal block is 10 nm;
• and
• a spacer layer,
• wherein the first metal block is a main control gate of the FET, the second metal block and the third metal block are used as two inducer gates of the FET, a gate voltage is accessed to the first metal block, the second metal block and the third metal block are used for generating a tunnel junction at a joint interface of the channel region and the drain region and are also used for realizing electrostatic doping of the channel region and the drain region under the induction of the gate-oxide inducer layer, such that the channel region and the drain region do not need to be chemically doped, and the spacer layer is used for isolating the first metal block from the second metal block and the third metal block to prevent the second metal block and the third metal block against interference from the gate voltage accessed to the first metal block.