Semiconductor device

A semiconductor device comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

• wherein one of a source and a drain of the first transistor is electrically connected to a first terminal,
• wherein a gate of the first transistor is electrically connected to a second terminal,
• wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
• wherein a drain of the second transistor is electrically connected to a third terminal,
• wherein a source of the second transistor is electrically connected to a drain of the fourth transistor,
• wherein one of a source and a drain of the third transistor is electrically connected to a fourth terminal,
• wherein a gate of the third transistor is electrically connected to a fifth terminal,
• wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,
• wherein a source of the fourth transistor is electrically connected to a drain of the fifth transistor, a drain of the sixth transistor, and a sixth terminal,
• wherein a gate of the fifth transistor is electrically connected to a seventh terminal,
• wherein the source of the fifth transistor is electrically connected to an eighth terminal,
• wherein a gate of the sixth transistor is electrically connected to a ninth terminal,
• wherein a source of the sixth transistor is electrically connected to a tenth terminal,
• wherein the second transistor comprises:
• a first conductive layer over a first layer;
• a first insulating layer over the first conductive layer;
• a second conductive layer over the first insulating layer;
• a first opening in the first insulating layer and the second conductive layer, the first opening overlapping with the first conductive layer;
• a first semiconductor layer comprising, in the first opening, a region in contact with the first conductive layer, a region in contact with the first insulating layer, and a region in contact with the second conductive layer, the first semiconductor layer being covered with a second insulating layer;
• and
• a third conductive layer comprising a region overlapping with the first semiconductor layer, the third conductive layer being over the second insulating layer,
• wherein the first conductive layer is electrically connected to the third terminal,
• wherein the second conductive layer is electrically connected to the drain of the fourth transistor,
• wherein the third conductive layer is electrically connected to the other of the source and the drain of the first transistor,
• wherein the fourth transistor comprises:
• a fourth conductive layer over the first layer;
• the first insulating layer over the fourth conductive layer;
• a fifth conductive layer over the first insulating layer;
• a second opening in the first insulating layer and the fifth conductive layer, the second opening overlapping with the fourth conductive layer;
• a second semiconductor layer comprising, in the second opening, a region in contact with the fourth conductive layer, a region in contact with the first insulating layer, and a region in contact with the fifth conductive layer, the second semiconductor layer being covered with the second insulating layer;
• and
• a sixth conductive layer comprising a region overlapping with the second semiconductor layer, the sixth conductive layer being over the second insulating layer,
• wherein the fifth conductive layer is electrically connected to the drain of the fifth transistor, and
• wherein the sixth conductive layer is electrically connected to the other of the source and the drain of the third transistor.