Semiconductor structure and memory
AssigneeChangxin Memory Technologies, Inc.
InventorsYicheng Gao, Jaeyong Cha
Life of this patent
Estimating the term…
Abstract
A semiconductor structure and a memory are provided. The semiconductor structure includes multiple active regions, a column selector and multiple bit lines. The column selector includes a first gate, a second gate, a third gate, a fourth gate and a connection line. The first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at the second node, and the connection line connects the first node and the second node. Each of the multiple bit lines includes a first portion, a second portion and a connection portion. Each of the multiple bit lines is connected to a respective one of the multiple active regions, the active regions connected to different bit lines among the multiple bit lines are different.
Claims14
A semiconductor structure, comprising:
- a plurality of active regions that are arranged in an array along a first direction and a second direction that are orthogonal, the first direction being parallel to a direction in which the plurality of active regions extend;
- a column selector, comprising:
- a first gate, a second gate, a third gate and a fourth gate, each of which is located on a respective one of four active regions adjacent to each other among the plurality of active regions, the first gate and the second gate extending along the second direction and intersecting at a first node, and the third gate and the fourth gate extending along the second direction and intersecting at a second node;
- and
- a connection line connecting the first node and the second node and extending along the first direction;
- and
- a plurality of bit lines that are arranged along the first direction, each of the plurality of bit lines comprising:
- a first portion and a second portion both extending along the second direction and being misaligned in the first direction, and
- a connection portion connecting the first portion and the second portion, wherein
- each of the plurality of bit lines is connected to a respective one of the plurality of the active regions, the active regions connected to different bit lines among the plurality of bit lines are different, and for each bit line, the first portion of the bit line and a second portion of an adjacent bit line are on a same straight line parallel to the second direction.
A memory, comprising a semiconductor structure, wherein the semiconductor structure includes:
- a plurality of active regions that are arranged in an array along a first direction and a second direction that are orthogonal, the first direction being parallel to a direction in which the plurality of active regions extend;
- a column selector, comprising:
- a first gate, a second gate, a third gate and a fourth gate, each of which is located on a respective one of four active regions adjacent to each other among the plurality of active regions, the first gate and the second gate extending along the second direction and intersecting at a first node, and the third gate and the fourth gate extending along the second direction and intersecting at a second node;
- and
- a connection line connecting the first node and the second node and extending along the first direction;
- and
- a plurality of bit lines that are arranged along the first direction, each of the plurality of bit lines comprising:
- a first portion and a second portion both extending along the second direction and being misaligned in the first direction, and
- a connection portion connecting the first portion and the second portion, wherein
- each of the plurality of bit lines is connected to a respective one of the plurality of the active regions, the active regions connected to different bit lines among the plurality of bit lines are different, and for each bit line, the first portion of the bit line and a second portion of an adjacent bit line are on a same straight line parallel to the second direction.
Dependencies are inferred from the claim text.