Semiconductor device having concave lower sidewall portion on gate structure

A semiconductor device comprising:

• a gate structure on a substrate, the gate structure including a first dielectric pattern containing silicon oxide;
• a first gate spacer contacting an upper portion of a sidewall of the gate structure, the first gate spacer including silicon nitride;
• and
• a second gate spacer contacting a lower portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer, the second gate spacer including silicon nitride,
• wherein a lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern, and the second gate spacer does not contact an upper portion of a sidewall of the first dielectric pattern but contacts a lower portion of the sidewall of the first dielectric pattern.

A semiconductor device comprising:

• a substrate including a cell region and a peripheral circuit region surrounding the cell region;
• a first active pattern on the cell region of the substrate;
• a second active pattern on the peripheral circuit region of the substrate;
• an isolation pattern covering sidewalls of the first active pattern and the second active pattern;
• a first gate structure buried at upper portions of the first active pattern and the isolation pattern, the first gate structure extending in a first direction substantially parallel to an upper surface of the substrate;
• a second gate structure on the second active pattern, a sidewall of the second gate structure including,
• a concave lower sidewall portion, and
• an upper sidewall portion that is vertical with respect to the upper surface of the substrate,
• a gate spacer structure including,
• a first gate spacer on the upper sidewall portion of the sidewall of the second gate structure,
• a second gate spacer on the concave lower sidewall portion of the sidewall of the second gate structure and an outer sidewall of the first gate spacer, the second gate spacer contacting a lower surface of the first gate spacer and including silicon nitride, and
• a third gate spacer on an outer sidewall of the second gate spacer;
• a bit line structure contacting a central upper surface of the first active pattern, the bit line structure extending in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction;
• a contact plug structure contacting each of opposite edge upper surfaces of the first active pattern;
• and
• a capacitor on the contact plug structure,
• wherein the second gate structure includes a first dielectric pattern adjacent to the upper surface of the substrate, and
• wherein the lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern.