Systems and methods for processing variable coding and modulation (VCM) based communication signals using feedforward carrier and timing recovery

A method for processing a digital bit stream, wherein the digital bit stream is a frame based digitized communication signal, the method comprising:

• dividing, at one or more processors, the digital bit stream into a plurality of data packets;
• detecting one or more frame boundaries in the plurality of data packets;
• performing a timing recovery error calculation on the plurality of data packets, the timing recovery error calculation comprising preforming a first phase locked loop (PLL) function on the plurality of data packets;
• performing, at a first processing block of the one or more processors, a timing recovery operation on a first portion of the plurality of data packets, based on the timing recovery error calculation;
• performing, at a second processing block of the one or more processors in parallel with the first processing block, the timing recovery operation on a second portion of the plurality of data packets, based on the timing recovery error calculation;
• combining the output of the first processing block and the output of the second processing block into blocks of time corrected symbols;
• and
• locating frame boundaries of the blocks of time corrected symbols by detecting a frame marker.

A system for processing a digital bit stream representative of a frame based digitized communication signal, the system comprising:

• a digitizer configured to convert a received analog signal into the digital bit stream;
• and
• one or more processors communicatively coupled to the digitizer, the one or more processors including a first processing block and a second processing block and configured to
• divide the digital bit stream into a plurality of data packets,
• detect one or more frame boundaries in the plurality of data packets,
• perform a timing recovery error calculation on the plurality of data packets, the timing recovery error calculation comprising preforming a first phase locked loop (PLL) function on the plurality of data packets,
• wherein the first processing block is configured to perform a timing recovery operation on a first portion of the plurality of data packets, based on the timing recovery error calculation,
• wherein the second processing block is coupled in parallel with the first processing block and configured to perform the timing recovery operation on a second portion of the plurality of data packets, based on the timing recovery error calculation,
• the one or more processors further configured to
• combine the output of the first processing block and the output of the second processing block into blocks of time corrected symbols, and
• locate frame boundaries of the blocks of time corrected symbols by detecting a frame marker.