Clock and multi-valued data signaling
AssigneeRambus Inc.
InventorsCarl W. Werner, Masum Hossain, Richelle L. Smith
Life of this patent
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Abstract
A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal is transitioned to indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.
Claims20
An integrated circuit, comprising:
- a first transmitter having a first output to transmit signals to indicate a first time sequence of binary valued bits comprising a first binary value and a second binary value;
- a second transmitter having a second output to transmit signals to indicate a second time sequence of binary valued bits comprising the first binary value and the second binary value;
- and
- transmitter control circuitry to control the first transmitter and the second transmitter to collectively transmit a plurality of bits per unit interval encoded as transition timings between the first output and the second output and to collectively transmit a clock signal.
An integrated circuit, comprising:
- a first receiver having a first input to receive signals that indicate a first time sequence of binary valued bits comprising a first binary value and a second binary value;
- a second receiver having a second input to receive signals that indicate a second time sequence of binary valued bits comprising the first binary value and the second binary value;
- and
- decoder circuitry to receive the first time sequence and the second time sequence and, based on transition timings between the first input and the second input, output a plurality of bits per unit interval and a clock signal.
A method of operating an integrated circuit, comprising:
- transmitting, via a first output, signals to indicate a first time sequence of binary valued bits comprising a first binary value and a second binary value;
- transmitting, via a second output, signals to indicate a second time sequence of binary valued bits comprising the first binary value and the second binary value;
- and
- controlling the first output and the second output to collectively transmit a plurality of bits per unit interval encoded as relationships between transition timings of the first output and the second output and to collectively transmit a clock signal.
Dependencies are inferred from the claim text.