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US 12,574,042 B2Granted
Analog-to-digital converter (ADC) architectures for high resolution and energy efficiency
AssigneeArizona Board of Regents on behalf of Arizona State University
InventorArindam Sanyal
Life of this patent
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Abstract
A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
Claims19
A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface, the device comprising:
- a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC;
- a second stage configured to obtain an output from the first stage and comprising a voltage-controlled oscillator (VCO)-ADC;
- and
- a calibration stage configured to obtain an output from the second stage and to estimate and track interstage gain across a process-voltage-temperature (PVT),
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the output of the first stage and the second stage to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
2 more elements
A low-pass and band-pass delta-sigma (AZ) analog-to-digital converter (ADC) system, the system comprising:
- a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC;
- a second stage configured to obtain an output from the first stage and comprising a voltage-controlled oscillator (VCO)-ADC;
- a calibration stage configured to obtain an output from the second stage and to estimate and track interstage gain across a process-voltage-temperature (PVT);
- and
- an artificial intelligence or a machine learning engine that is programmed to communicate with either the first stage or the second stage,
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the output of the first stage and the second stage to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
3 more elements
A radio comprising:
- band-pass delta-sigma (AZ) analog-to-digital converter (ADC);
- a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC;
- and
- a second stage configured to obtain an output from the first stage and comprising a voltage-controlled oscillator (VCO)-ADC;
- and
- a calibration stage configured to obtain an output from the second stage and to estimate and track interstage gain across a process-voltage-temperature (PVT),
- wherein the calibration stage comprises a foreground calibration stage that operates only at device start up to receive the output of the first stage and the second stage to extract an initial interstage gain error and corrects the initial interstage gain error and a background calibration stage that corrects continued instances of the interstage gain error that varies with time, voltage, and temperature of the device.
4 more elements
Dependencies are inferred from the claim text.