Quantization error and spur mitigation in a digital phase-locked loop

A digital phase-locked loop (DPLL), comprising:

• a dithering source to provide a dithering signal that causes periodicity to be eliminated from a quantization error of a primary delta-sigma modulator (DSM) of the DPLL;
• a primary signal path comprising the primary DSM;
• a first auxiliary signal path comprising a first auxiliary DSM associated with cancelling an effect of the dithering signal on an output signal of the DPLL;
• and
• a second auxiliary signal path comprising a second auxiliary DSM associated with cancelling an effect of the quantization error of the primary DSM on the output signal of the DPLL.

A digital phase-locked loop (DPLL), comprising:

• a dithering source to provide a dithering signal, wherein the dithering signal is on an order of up to one integer bit on a set of fractional bits of a modulation signal;
• a digitally controlled oscillator (DCO) to generate a DPLL output signal based at least in part on the modulation signal;
• a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal;
• and
• a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association cancelling an effect of at least a quantization error of the primary DSM on the DPLL output signal.