Schottky-CMOS static random-access memory

A static random access memory (SRAM) array, comprising:

• a substrate;
• and
• a plurality of bit cells formed on the substrate, wherein at least one of the plurality of bit cells further including:
• a latch formed from two cross-coupled inverters, the two cross-coupled inverters including a first inverter and a second inverter that are driven between a word line write signal and a word line read signal, wherein an input of the first inverter is cross-coupled to an output of the second inverter, and an output of the first inverter is cross-coupled to an input of the second inverter;
• and
• a first Schottky barrier diode (SBD) and a second SBD, wherein the first SBD are electrically coupled between the output of the first inverter and a first bit signal, and the second SBD are electrically coupled between the output of the second inverter and a second bit signal, the first and second bit signals being complementary signals, wherein each of the first and second inverters includes two complementary metal oxide semiconductor (CMOS) transistors, and the first SBD is integrated in a substantially shallow diffusion bed associated with a drain of a first CMOS transistor of the first and second inverters.