Transistor assemblies with gate current shunting capability, and associated methods

A method for shunting current away from a gate of a first N-channel field effect transistor (FET) including a drain electrically coupled to a first power supply, the method comprising:

• charging a gate-to-source capacitance of a second N-channel FET via a capacitor electrically coupled to a gate of the second N-channel FET;
• shunting current away from the gate of the first N-channel FET via the second N-channel FET, a drain of the second N-channel FET being electrically coupled to the gate of the first N-channel FET;
• and
• discharging the gate-to-source capacitance of the second N-channel FET in response to a second power supply becoming active.

An electrical circuit configured to be electrically coupled to a load, comprising:

• a first power supply;
• a second power supply;
• and
• a transistor assembly, including:
• a first field effect transistor (FET) and a second FET, the first FET and the second FET being configured to be electrically coupled in series between the first power supply and the load, each of the first FET and the second FET being a respective N-channel FET,
• a control circuit at least partially powered by the second power supply, the control circuit being configured to control a respective operating state of each of the first FET and the second FET, and
• a capacitor and a third FET collectively configured to shunt current away from a gate of the first FET during a pre-power operating state of the transistor assembly characterized at least partially by (a) the first power supply being active and (b) the second power supply being inactive.