Serdes transmitter and receiver utilizing single frequency phase amplitude modulation
AssigneeTexas Milkyway Inc.
InventorSheau-Jiung Lee
Life of this patent
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Abstract
Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.
Claims20
A transmitter comprising:
- a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values;
- a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents;
- a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal;
- wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.
A receiver comprising:
- a demodulation and amplifier block to receive a differential signal and to generate a plurality of pairs of currents;
- a plurality of comparator and calibration blocks, each of the plurality of comparator and calibration blocks receiving one of the plurality of pairs of currents to generate a comparator output;
- and
- a demapping block to receive the comparator output from each of the plurality of comparator and calibration blocks to generate a clock signal and a two-bit data signal.
A system comprising:
- a transmitter comprising:
- a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values;
- a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents;
- a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal;
- wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal;
- a receiver comprising:
- a demodulation and amplifier block to receive a differential signal and to generate a plurality of pairs of currents;
- a plurality of comparator and calibration blocks, each of the plurality of comparator and calibration blocks receiving one of the plurality of pairs of currents to generate a comparator output;
- and
- a demapping block to receive the comparator output from each of the plurality of comparator and calibration blocks to generate the clock signal and the two-bit data signal;
- and
- an interface coupling the transmitter and the receiver.
A method comprising:
- generating, by a transmitter, a differential signal in response to a clock signal and a two-bit data signal wherein the differential signal is a single frequency pulse amplitude modulated signal and wherein the single frequency is a frequency of the clock signal;
- receiving, by a receiver, the differential signal;
- and
- generating, by the receiver, the clock signal and the two-bit data signal in response to the differential signal.
Dependencies are inferred from the claim text.