Sense amplifier and output latch circuit for testing

A memory circuit, comprising:

• a memory array including a memory bit cell coupled between a first data line and a second data line;
• and
• an input/output circuit operatively coupled to the memory array and including:
• a bypass circuit configured to directly receive a data signal and indirectly receive a write enable signal through an XOR gate, wherein the XOR gate generates a bypass data signal based on the data signal and the write enable signal;
• a first latch coupled to the first data line and the second data line, and including a first switch and a second switch, wherein the first switch is configured to selectively couple the bypass data signal to the first date line and the second switch is configured to selectively couple an inverse of the bypass data signal to the second data line;
• and
• a second latch operatively coupled to the first latch and configured to generate a data output signal based on a voltage level presented on the second data line.

A method for operating a memory circuit, comprising:

• directly receiving a data signal and indirectly receiving a write enable signal through an XOR gate, wherein the XOR gate generates a bypass data signal based on the data signal and the write enable signal;
• transmitting, to a master latch, the bypass data signal, wherein the master latch is coupled to a memory bit cell through a first data line and a second data line;
• transmitting, to the master latch, a logic inverse of the bypass data signal;
• and
• generating, from a shadow latch, a data output signal based on a voltage level presented on the second data line.