Four-transistor static random access memory cell with enhanced data retention
AssigneeFlashsilicon Incorporation
InventorLee Wang
Life of this patent
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Abstract
A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage Vstdf and a difference voltage (VDD−Vstdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<Vstdf<VDD.
Claims15
A static random access memory (SRAM) cell comprising:
- a cross-coupled pair of PMOS transistors coupled to a supply voltage rail, a first storage node and a second storage node;
- and
- two NMOS transistors coupled to a word line, the first and the second storage nodes and a bit line pair;
- wherein when the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage Vstdf and a difference voltage (VDD−Vstdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period;
- and
- wherein VDD denotes a supply voltage at the second storage node and 0<Vstdf<VDD.
Dependencies are inferred from the claim text.