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US 12,573,448 B2Granted
DRAM device with multiple voltage domains
AssigneeRambus Inc.
InventorThomas Vogelsang
Life of this patent
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Abstract
A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.
Claims20
A memory device, comprising:
- a memory array comprising memory cells coupled to bitlines and sense amplifier circuits coupled to the bitlines;
- the bitlines to operate, in a normal operating mode that is a non-test-mode, using a first voltage;
- the sense amplifier circuits to, in the normal operating mode and in order to deactivate cross-coupled inverters of the sense amplifier circuits that evaluate voltages on the bitlines, receive a first field-effect transistor (FET) gate control signal with the first voltage and a second FET gate control signal with a second voltage, and also to, in the normal operating mode and in order to activate the cross-coupled inverters, receive the first FET gate control signal with the second voltage and the second FET gate control signal with a third voltage, the third voltage being less than the first voltage, the sense amplifier circuits to, in the normal operating mode, apply the first voltage to the bitlines;
- and
- digital logic circuitry to control the sense amplifier circuits and operate, in the normal operating mode, using the third voltage as its supply voltage.
2 more elements
An integrated circuit, comprising:
- a memory array comprising memory cells coupled with bitlines and sense amplifier circuits coupled with the bitlines;
- the sense amplifier circuits to, in a normal operating mode and in order to deactivate cross-coupled inverters of the sense amplifier circuits that evaluate voltages on the bitlines, receive a first field effect transistor (FET) gate control signal with a first voltage and a second FET gate control signal with a second voltage, and to also, in the normal operating mode and in order to activate the cross-coupled inverters, receive the first FET gate control signal with the second voltage and the second FET gate control signal with a third voltage, the first voltage to be greater than the third voltage, the first voltage to be applied, by the sense amplifier circuits, to the bitlines;
- and
- digital logic circuitry to control the sense amplifier circuits and operate, in the normal operating mode, using the third voltage as its supply voltage.
1 more element
A memory device, comprising:
- digital logic circuitry to, in a normal operating mode, at least process column addresses and row addresses to access data stored in a memory array and to control one or more elements of sense amplifier circuits that are part of the memory array;
- the memory array comprising memory cells coupled with bitlines and coupled with the sense amplifier circuits;
- the sense amplifier circuit to, in the normal operating mode and in order to deactivate cross-coupled inverters of the sense amplifier circuits that evaluate voltages on the bitlines, receive a first field effect transistor (FET) gate control signal having a first voltage and a second FET gate control signal having a second voltage, and also to, in the normal operating mode and in order to activate the cross-coupled inverters, receive the first FET gate control signal with the second voltage and the second FET gate control signal with a third voltage, the third voltage to be less than the first voltage, the sense amplifier circuits to apply the first voltage to the bitlines, and
- the digital logic circuitry to operate, in the normal operating mode that is a non-test mode, using the third voltage as the digital logic circuitry's supply voltage.
1 more element
Dependencies are inferred from the claim text.