Display device

A display device comprising:

• a semiconductor chip, mounted in a frame region disposed around a display region of a display panel, to supply a video signal to a plurality of pixels disposed in the display region of the display panel;
• a peripheral circuit formed in the frame region to protect or inspect the plurality of pixels in the display region before the semiconductor chip is mounted in the frame region;
• a first high power source line and a second high power source line;
• and
• a first low power source line and a second low power source line, each having a potential lower than a potential of a respective one of the first high power source line and the second high power source line,
• wherein the display panel includes a plurality of panel terminals to which a plurality of output terminals of the semiconductor chip is bonded, respectively,
• the plurality of panel terminals is arranged in accordance with a staggered arrangement in which the plurality of panel terminals is arranged in directions oblique to each other,
• the peripheral circuit includes a plurality of peripheral circuit elements arranged in accordance with the staggered arrangement to correspond to the plurality of panel terminals, respectively,
• each of the plurality of pixels includes a first subpixel configured to emit a first luminescent color light, a second subpixel configured to emit a second luminescent color light, and a third subpixel configured to emit a third luminescent color light,
• some of the plurality of peripheral circuit elements are a plurality of first elements corresponding to the first subpixel,
• another some of the plurality of peripheral circuit elements are a plurality of second elements corresponding to the second subpixel,
• still another some of the plurality of peripheral circuit elements are a plurality of third elements corresponding to the third subpixel,
• the plurality of first elements is arranged in a first row of the staggered arrangement,
• the plurality of second elements is arranged in a second row of the staggered arrangement,
• the plurality of third elements is arranged in a third row of the staggered arrangement,
• the first low power source line, the first row of the staggered arrangement, the first high power source line, the second row of the staggered arrangement, the second low power source line, the third row of the staggered arrangement, and the second high power source line are arranged in this order,
• the first low power source line is connected to the plurality of first elements,
• the first high power source line is connected to the plurality of first elements and the plurality of second elements,
• the second low power source line is connected to the plurality of second elements and the plurality of third elements, and
• the second high power source line is connected to the plurality of third elements.