Core criticality performance enhancements
AssigneeApple Inc.
InventorsWei-Han Lien, Edvin Catovic, Nikhil Gupta, Mridul Agarwal, Haoyan Jia, Ethan R. Schuchman
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Abstract
Techniques are disclosed relating to critical path identification and prioritization. In some embodiments, criticality detection circuitry is configured to sparsely assign tokens to a subset of instructions to be executed by pipeline circuitry, track a distance between execution of the instruction and execution of one or more instructions that depend on the instruction, and train instructions as predicted-critical or not based on tracked distances. In some embodiments, scheduling circuitry is configured to prioritize predicted-critical instructions over other instructions for issuance.
Claims19
An apparatus, comprising:
- processor pipeline circuitry configured to execute program instructions out of program order;
- criticality detection circuitry configured to:
- assign tokens to only a subset of instructions to be executed by the processor pipeline circuitry;
- track, using a token assigned to a first instruction, a distance corresponding to a number of cycles between execution of the first instruction and execution of one or more instructions that depend on the first instruction, including to:
- detect that a second instruction of the one or more instructions depends on the first instruction;
- determine that the first instruction generates a last-arriving operand of the second instruction;
- and
- pass the token from the first instruction to the second instruction based on the determination;
- and
- based on whether one or more tracked distances meet a distance threshold using tokens, train the first instruction as predicted critical;
- and
- scheduling circuitry configured to prioritize predicted-critical instructions over other instructions for issuance to execution circuitry.
A method, comprising:
- executing program instructions out of program order;
- assigning tokens to only a subset of instructions to be executed;
- tracking, using the token assigned to first instruction, a distance corresponding to a number of cycles between execution of the first instruction and execution of one or more instructions that depend on the first instruction, including:
- detecting that a second instruction of the one or more instructions depends on the first instruction;
- determining that the first instruction generates a last-arriving operand of the second instruction;
- and
- passing the token from the first instruction to the second instruction based on the determination;
- training the first instruction as predicted-critical based on whether one or more tracked distances meet a distance threshold using tokens;
- and
- prioritizing predicted-critical instructions over other instructions for issuance.
A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
- processor pipeline circuitry configured to execute program instructions out of program order;
- criticality detection circuitry configured to:
- assign tokens to only a subset of instructions to be executed by the processor pipeline circuitry;
- track, using a token assigned to a first instruction, a distance corresponding to a number of cycles between execution of the first instruction and execution of one or more instructions that depend on the first instruction, including to:
- detect that a second instruction of the one or more instructions depends on the first instruction;
- determine that the first instruction generates a last-arriving operand of the second instruction;
- and
- pass the token from the first instruction to the second instruction based on the determination;
- and
- based on whether one or more tracked distances meet a distance threshold using tokens, train the first instruction as predicted critical;
- and
- scheduling circuitry configured to prioritize predicted-critical instructions over other instructions for issuance to execution circuitry.
Dependencies are inferred from the claim text.