US 12,572,498 B2 · Secure serial peripheral interface communication

Abstract

This document discloses aspects of secure serial peripheral interface (SPI) communication. In some aspects, a secure SPI communication module monitors communications transmitted by a host to a peripheral block that is coupled to the host via a SPI interconnect. The module compares respective commands of the communications sent by the host to information indicating commands that the peripheral block is not authorized to execute. Based on the comparing, the module determines that one of the respective commands is one of the commands that the peripheral block is not authorized to execute. The module then prevents the peripheral block from receiving at least a portion of the respective command of the communication. By so doing, the module can prevent the peripheral block from executing unauthorized commands, which may compromise security of the peripheral block.

Claims20

Dependent claims

A method implemented by security circuitry associated with a host of a system for secure serial peripheral interface communication, the method comprising:

monitoring communications transmitted by the host to a peripheral block of the system that is coupled to the host via a serial peripheral interface (SPI) interconnect;
comparing respective commands of the communications sent by the host to information indicating which commands the peripheral block is not authorized to execute;
determining, based on the comparing, that one of the respective commands comprises a write-status-register command that the peripheral block is not authorized to execute;
and
in response to determining that the peripheral block is not authorized to execute the write-status-register command, altering the write-status-register command to prevent the write-status-register command from altering a status register of the peripheral block.

2 more elements

An integrated circuit including circuitry for secure serial peripheral interface communication, the circuitry comprising:

a host with a functional core;
at least one peripheral block;
a serial peripheral interface (SPI) interconnect coupling the host and the at least one peripheral block;
and
a secure SPI communication module operably coupled with the SPI interconnect and configured to:
monitor communications transmitted by the host to a peripheral block of the at least one peripheral block of the integrated circuit that is coupled to the host via the serial peripheral interface (SPI) interconnect;
compare respective commands of the communications sent by the host to information indicating which commands the peripheral block is not authorized to execute;
determine, based on the comparing, that one of the respective commands comprises a write-status-register command that the peripheral block is not authorized to execute;
and
in response to the determination that the peripheral block is not authorized to execute the write-status-register command, alter the write-status-register command to prevent the write-status-register command from altering a status register of the peripheral block.

7 more elements

Dependencies are inferred from the claim text.

Secure serial peripheral interface communication

Life of this patent

Secure serial peripheral interface communication

Life of this patent

Abstract

Claims20