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US 12,572,493 B2Granted
Electronic device having a plurality of chiplets
AssigneeRebellions Inc.
InventorsYoung-Jae Jin, Miock Chi
Life of this patent
Estimating the term…
Abstract
Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.
Claims17
An electronic device, comprising:
- a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
- a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module;
- and
- the system bus comprises a switch logic comprising a first logic, wherein
- in response to determining that a communication failure occurs between the first chiplet and the second chiplet, the switch logic is activated to change at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet, wherein the first logic is activated in response to determining that a disconnection occurs in at least one path of the transfer path coupled to the switch logic, wherein the transfer path comprises a first path through which information is transmitted to the switch logic, a second path through which the information is transmitted from the switch logic to the first interconnect interface, and a third path through which the information is transmitted from the switch logic to the second interconnect interface, and wherein the first logic comprises a logic that:
- connects the first path to the third path in response to determining that a disconnection occurs in at least a part of the second path, and
- connects the first path to the second path in response to determining that a disconnection occurs in at least a part of the third path.
4 more elements
An electronic device, comprising:
- a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
- a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module;
- and
- the system bus comprises a distributor, wherein
- in response to determining a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
- the transfer path comprises a fourth path through which information is transmitted to the distributor, a fifth path through which the information is transmitted from the distributor to the first interconnect interface, and a sixth path through which the information is transmitted from the distributor to the second interconnect interface, and
- the distributor connects the fifth path or the sixth path to the fourth path in response to determining that no communication failure has occurred.
4 more elements
An electronic device, comprising:
- a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
- and
- a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module;
- wherein
- in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
- the information transmitted to the second chiplet using the first interconnect interface is transmitted based on a first clock,
- the information transmitted to the second chiplet using the second interconnect interface is transmitted based on a second clock, and
- the first clock and the second clock are different from each other.
5 more elements
An electronic device, comprising:
- a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
- and
- a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module, wherein
- in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
- the first interconnect module and the second interconnect module are configured to communicate with each other based on a first protocol, and
- at least one of the first chiplet or the second chiplet comprises a third interconnect module configured to communicate with a host based on a second protocol.
3 more elements
Dependencies are inferred from the claim text.