Memory management method and device, chip, and traffic apparatus
AssigneeBeijing SemiDrive Technology Ltd.
InventorXiaofeng Xu
Life of this patent
Estimating the term…
Abstract
A memory management method includes receiving, by a first operating system, a memory scheduling request sent by at least one second operating system through an inter-core communication channel, determining, by the first operating system, a target memory priority of each second processor corresponding to the second operating system based on the memory scheduling request, and assigning, by the first operating system, a memory bandwidth to the second operating system based on the target memory priority of the second processor. The memory scheduling request is used to request a memory bandwidth required by the second operating system. Each operating system is configured to run on a hardware set of a system-on-chip (SoC).
Claims20
A memory management method comprising:
- receiving, by a first operating system to which a first processor corresponds, a memory scheduling request sent by a second operating system through an inter-core communication channel, the memory scheduling request being used to request a memory bandwidth required by the second operating system;
- determining, by the first operating system, a target memory priority of a second processor corresponding to the second operating system based on the memory scheduling request;
- and
- assigning, by the first operating system, the memory bandwidth to the second operating system based on the target memory priority of the second processor;
- wherein each operating system is configured to run on a hardware set of a system-on-chip (SoC).
A memory management running a first operating system comprising:
- a reception module configured to receive a memory scheduling request sent by a second operating system through an inter-core communication channel, the memory scheduling request being used to request a memory bandwidth required by the second operating system;
- a determination module configured to determine a target memory priority of a second processor corresponding to the second operating system based on the memory scheduling request;
- and
- an assignment module configured to assign the memory bandwidth to the second operating system based on the target memory priority of the second processor;
- wherein each operating system is configured to run on a hardware set of a system-on-chip (SoC).
A chip comprising:
- a bus;
- one or more processors;
- and
- one or more memories communicating with the one or more processors through the bus and storing executable instructions that, when executed by the one or more processors, cause the one or more processors to:
- receive, by a first operating system to which a first processor corresponds, a memory scheduling request sent by a second operating system through an inter-core communication channel, the memory scheduling request being used to request a memory bandwidth required by the second operating system;
- determine, by the first operating system, a target memory priority of a second processor corresponding to the second operating system based on the memory scheduling request;
- and
- assign, by the first operating system, the memory bandwidth to the second operating system based on the target memory priority of the second processor;
- wherein each operating system is configured to run on a hardware set of a system-on-chip (SoC).
Dependencies are inferred from the claim text.