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US 12,572,417 B2Granted
Translation cache and configurable ECC memory for reducing ECC memory overhead
AssigneeIntel Corporation
InventorsDuane E. Galbi, Wim Heirman, Dimitrios Ziakas
Life of this patent
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Abstract
A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).
Claims20
An apparatus comprising:
- a circuitry coupled to a memory subsystem having a memory cache line width, the circuitry to:
- translate cached data with the memory cache line width into a translation cache of one or more cache sub-lines matching an internal processor cache line width, each cache sub-line including an error checking and correction (ECC) data to error check and correct the cached data in the cache sub-line,
- hold any of the one or more cache sub-lines in the translation cache to allow sufficient time to any of write and read all cache sub-lines for the cached data before the translation cache is flushed;
- and
- wherein the cache sub-lines, including the ECC data, are stored in corresponding parts of memory devices of the memory subsystem to reduce memory device overhead to store ECC data.
2 more elements
A system comprising:
- a processor;
- a memory subsystem of memory devices in which to store cached data, including an error checking and correction (ECC) data, the memory subsystem having a memory cache line width;
- a translation cache between the processor and the memory subsystem;
- and
- the processor to manage the translation cache including to:
- use any of a burst length or corresponding parts of the memory devices to access the cached data to determine which portion of the cached data to process in the translation cache,
- receive one or more portions of the cached data in the translation cache, the cached data including the ECC data to correct each of the one or more portions of the cached data,
- determine that the one or more portions of the cached data exceed an internal processor cache line width, and
- process the one or more portions of the cached data to reduce overhead to store the ECC data in the memory subsystem, including to:
- translate the one or more portions of the cached data into a translation cache of one or more cache sub-lines matching the internal processor cache line width, each cache sub-line including the ECC data to error check and correct the cached data in the cache sub-line, and
- hold any of the one or more cache sub-lines in the translation cache to allow sufficient time for the processor to any of write and read all cache sub-lines for the cached data before the translation cache is flushed.
8 more elements
A memory comprising:
- devices to store data in corresponding parts of the devices;
- the devices configurable to reduce overhead to store an error checking and correction (ECC) data to correct the data, including to store the ECC data in a corresponding part of a separate device;
- the corresponding parts including any same one of an upper, lower, left and right parts of the devices and the separate device;
- and
- circuitry coupled to a translation cache between the devices and a processor having an internal cache line width less than a memory cache line width of the devices, the circuitry to:
- access cached data stored in the corresponding parts of the devices responsive to a request from the processor,
- determine which portion of the cached data to process in the translation cache,
- receive one or more portions of the cached data in the translation cache, the cached data including the ECC data to correct each of the one or more portions of the cached data,
- determine that the one or more portions of the cached data exceed the internal processor cache line width, and
- process the one or more portions of the cached data to reduce overhead for storing the ECC data, including to:
- translate the one or more portions of the cached data into a translation cache of one or more cache sub-lines matching the internal processor cache line width, each cache sub-line including the ECC data to error check and correct the cached data in the cache sub-line, and
- hold any of the one or more cache sub-lines in the translation cache to allow sufficient time for the processor to any of write and read all cache sub-lines for the cached data before the translation cache is flushed.
9 more elements
Dependencies are inferred from the claim text.