Processor and method for executing a looping code segment with zero overhead

A method for executing a looping code segment, the method comprising:

• executing a loop branch instruction of the looping code segment, the looping code segment comprising a first loop instruction at a first loop instruction address and a last loop instruction at a last loop instruction address,
• wherein the loop branch instruction directs execution to the first loop instruction address upon satisfaction of a branch condition, and
• wherein the first loop instruction address is not sequential to an address of the loop branch instruction;
• storing a branch identifier associated with the loop branch instruction in a branch target address predictor;
• storing a first loop instruction associated with the first loop instruction address in the branch target address predictor;
• storing a second loop instruction address in the branch target address predictor,
• wherein the second loop instruction address is in sequence with the first loop instruction address;
• and
• executing at least one iteration of the looping code segment with zero overhead, in an instance in which the branch condition is met,
• wherein executing the looping code segment with zero overhead comprises executing the first loop instruction during an execution clock cycle immediately following execution of the last loop instruction.

A processor comprising:

• a pipelined architecture configured to execute one or more instructions on an execute clock cycle;
• a looping code segment comprising a first loop instruction at a first loop instruction address, a second loop instruction at a second loop instruction address, a last loop instruction at a last loop instruction address, and a loop branch instruction;
• and
• a branch target address predictor, comprising:
• a first memory portion configured to store a valid branch identifier, indicating a branch identifier is initialized;
• a second memory portion configured to store a branch taken indicator indicating a likelihood that the loop branch instruction directs execution to the first loop instruction;
• a third memory portion configured to store the branch identifier;
• a fourth memory portion configured to store a variable target address instruction,
• wherein the fourth memory portion stores the first loop instruction address after a first iteration of the looping code segment, and
• wherein the fourth memory portion stores the second loop instruction address after two or more iterations of the looping code segment;
• a fifth memory portion configured to store one or more first instruction operational codes associated with the first loop instruction;
• and
• a sixth memory portion configured to store a valid opcode identifier, indicating the one or more first instruction operational codes stored in the fifth memory portion are initialized,
• wherein the branch target address predictor enables the pipelined architecture to execute the last loop instruction and the first loop instruction on consecutive execute clock cycles.