Back to results
US 12,572,360 B2Granted
Cache preload operations using streaming engine
AssigneeTexas Instruments Incorporated
InventorsJoseph Raymond Michael Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad, David M. Thompson
Life of this patent
Estimating the term…
Abstract
A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.
Claims20
A device comprising:
- a processor;
- a cache memory;
- and
- a memory access circuit coupled to the processor and the cache memory, wherein the memory access circuit is configured to:
- receive, from the processor, a cache management instruction that includes:
- a base address;
- an opcode;
- and
- a data size;
- and
- preload the cache memory with data based on the cache management instruction, wherein the cache management instruction specifies whether a subsequent operation on the data preloaded into the cache memory is a read or a write.
8 more elements
A system comprising:
- a processor;
- a cache memory coupled to the processor;
- and
- a memory access component coupled to the processor and the cache memory, wherein the memory access component is operable to:
- receive a first instruction to open a data-less stream;
- preload the cache memory with data based on a cache management instruction, wherein the cache management instruction specifies whether a subsequent operation on the data preloaded into the cache memory is a read or a write;
- and
- in response to completion of the preload, close the data-less stream.
5 more elements
A method comprising:
- receiving, by a memory access component, a first instruction to open a data-less stream;
- in response to the first instruction:
- preloading, by the memory access component, a cache memory with data based on a cache management instruction, the cache management instruction specifying whether a subsequent operation on the data preloaded into the cache memory is a read or a write;
- and
- asserting, by the memory access component, a coherence active signal to a processor;
- and
- in response to completing the preloading, closing, by the memory access component, the data-less stream.
4 more elements
Dependencies are inferred from the claim text.