Geometric loading effect correction for lithography
AssigneeD2S, Inc.
InventorsAkira Fujimura, Abhishek Shendre
Life of this patent
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Abstract
Methods and systems involve a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges. Methods and systems also involve determining a neighborhood open area density for the plurality of patterns; determining a geometric loading effect correction, wherein the geometric loading effect correction comprises a calculated offset from an edge of a pattern in the plurality of patterns, and wherein the calculated offset is determined using the neighborhood open area density; and adjusting the edge of the pattern in the plurality of patterns using the geometric loading effect correction.
Claims19
A method for semiconductor manufacture comprising:
- inputting a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges;
- determining a neighborhood open area density for the plurality of patterns;
- determining a geometric loading effect correction (gLEC), wherein the geometric loading effect correction comprises a calculated offset from an edge of a pattern in the plurality of patterns, and wherein the calculated offset is determined using the neighborhood open area density;
- and
- adjusting the edge of the pattern in the plurality of patterns using the geometric loading effect correction to counteract a loading effect, wherein the loading effect is a difference in an amount of etching that occurs based on the neighborhood open area density.
A system for semiconductor manufacture comprising:
- a device configured to receive a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges;
- a device configured to determine a neighborhood open area density for the plurality of patterns;
- a device configured to determine a geometric loading effect correction, wherein the geometric loading effect correction comprises a calculated offset from an edge of a pattern in the plurality of patterns, and wherein the calculated offset is determined using the neighborhood open area density;
- and
- a device configured to adjust the edge of the pattern in the plurality of patterns using the geometric loading effect correction to counteract a loading effect, wherein the loading effect is a difference in an amount of etching that occurs based on the neighborhood open area density.
A method for manufacturing a semiconductor device comprising:
- determining a neighborhood open area density for a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges;
- determining a geometric loading effect correction, wherein the geometric loading effect correction comprises a calculated offset from an edge of a pattern in the plurality of patterns, and wherein the calculated offset is determined using the neighborhood open area density;
- adjusting the edge of the pattern in the plurality of patterns using the geometric loading effect correction to counteract a loading effect, wherein the loading effect is a difference in an amount of etching that occurs based on the neighborhood open area density;
- and
- forming the adjusted edge on the semiconductor device.
Dependencies are inferred from the claim text.