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US 12,571,840 B2Granted
Array of through-silicon via contact points on a semiconductor die
AssigneeTexas Instruments Incorporated
InventorsLee D. Whetsel, Baher S. Haroun
Life of this patent
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Abstract
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
Claims20
A semiconductor die comprising:
- a plurality of signal through-silicon-vias (TSVs);
- a test circuit coupled to the plurality of the signal TSVs;
- a reference voltage line coupled to the test circuit and operable to provide a reference voltage;
- and
- a surface including:
- a plurality of first contact points arranged in an array, wherein each of the first contact points is coupled to a corresponding signal TSV of the plurality of signal TSVs;
- a second contact point separate from the plurality of first contact points, disposed in the array, and coupled to the reference voltage line;
- a ground contact point separate from the second contact point and coupled to the test circuit;
- and
- a power contact point separate from the second contact point, separate from the ground contact point, and coupled to the test circuit.
7 more elements
A semiconductor die comprising:
- a plurality of signal through-silicon-vias (TSVs);
- a power TSV;
- a ground TSV;
- a test circuit coupled to each of the plurality of the signal TSVs, wherein the test circuit includes a stimulus current source configurable to generate a stimulus current on a first TSV of the plurality of TSVs, and wherein the test circuit further includes a comparator coupled to the first TSV;
- a reference voltage line coupled to the comparator and operable to provide a reference voltage;
- and
- a surface including:
- a plurality of first contact points arranged in an array, wherein each of the first contact points is coupled to a corresponding signal TSV of the plurality of signal TSVs;
- a second contact point disposed within the array and coupled to the reference voltage line;
- a third contact point disposed in a first corner portion of the array and coupled to the power TSV;
- and
- a fourth contact point disposed in a second corner portion of the array and coupled to the ground TSV.
9 more elements
A semiconductor die comprising:
- a plurality of signal through-silicon-vias (TSVs);
- a power TSV;
- a ground TSV;
- a test circuit coupled to each of the plurality of the signal TSVs, wherein the test circuit includes a stimulus voltage source configurable to generate a stimulus voltage on a first TSV of the plurality of TSVs, and wherein the test circuit further includes a comparator coupled to the first TSV;
- a reference voltage line coupled to the comparator and operable to provide a reference voltage;
- and
- a surface including:
- a plurality of first contact points arranged in an array, wherein each of the first contact points is coupled to a corresponding signal TSV of the plurality of signal TSVs;
- a second contact point disposed within the array and coupled to the reference voltage line;
- a third contact point disposed in a first corner portion of the array and coupled to the power TSV;
- and
- a fourth contact point disposed in a second corner portion of the array and coupled to the ground TSV.
9 more elements
Dependencies are inferred from the claim text.