Inspection apparatus and method

An apparatus, comprising:

• a device-under-test (DUT) board configured to support a first semiconductor device formed by a semiconductor process, the first semiconductor device including a backside interconnection structure;
• an electron beam generator configured to direct an electron beam toward a frontside of the first semiconductor device;
• an electrical signal source configured to apply an electrical signal to an electrical contact of the first semiconductor device via an electrical path, the electrical path extending through a shunt board attached to a switchable interface trace bank of the DUT board, the electrical contact being associated with a position at which the electron beam impinges;
• a controller operatively coupled to the electron beam generator and the electrical signal source and configured to:
• receive output signals generated during electron beam irradiation of the first semiconductor device;
• generate a physical failure analysis model for the first semiconductor device;
• evaluate the physical failure analysis model together with data from the semiconductor process to produce at least one revised process parameter selected from deposition pressure, deposition temperature, precursor flow rate, or epitaxial-growth duration;
• and
• a semiconductor-fabrication tool set comprising one or more deposition chambers, etch chambers, anneal furnaces, or epitaxial-growth chambers, the tool set being operable to execute a revised semiconductor manufacturing process that incorporates the at least one revised process parameter to form a second semiconductor device including a backside interconnection structure comparable to that of the first semiconductor device.

A method for generating a revised semiconductor process, comprising:

• providing a first semiconductor device having a backside interconnection structure, the first semiconductor device being produced by an initial semiconductor process;
• performing an inspection process comprising:
• directing an electron beam toward a selected region on a frontside of the first semiconductor device;
• and
• concurrently applying an electrical signal to an electrical contact associated with the selected region through an electrical path extending through a shunt board coupled to a switchable interface trace bank;
• generating a physical failure analysis model for the first semiconductor device based on responses elicited during the inspection process;
• evaluating the physical failure analysis model together with the initial semiconductor process and, based on the evaluation, revising at least one revised process parameter selected from deposition pressure, deposition temperature, precursor flow rate, or epitaxial-growth duration;
• and
• executing a revised semiconductor manufacturing process that incorporates the at least one revised process parameter to fabricate a second semiconductor device having a backside interconnection structure comparable to that of the first semiconductor device.