Stacked package structure including a chip disposed on a redistribution layer and a molding layer comprises a recess

A stacked packaging structure, comprising:

• an upper redistribution layer comprising a first surface and a second surface opposite to the first surface;
• a first chip disposed on the first surface of the upper redistribution layer and electrically connected to the upper redistribution layer;
• and
• an upper molding layer disposed on the first chip and the first surface of the upper redistribution layer, and configured to encapsulate the first chip, wherein the upper molding layer comprises a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is formed around a periphery of the upper molding layer;
• wherein no additional elements are provided between the upper molding layer and the upper redistribution layer at a position corresponding to the recess.