Wafer-level-package device with peripheral side wall protection
AssigneePanjit International Inc.
InventorsChung-Hsiung Ho, Wen-Liang Huang, Jeng-Sian Wu
Life of this patent
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Abstract
A wafer-level-package device with peripheral side wall protection has a die, multiple conductive bumps, and a protection layer. The die has a top surface, a bottom surface, and a peripheral side wall. A cavity is formed on the peripheral side wall of the die and around the die. The multiple conductive bumps are mounted on at least one of the top surface and the bottom surface of the die. The protection layer covers the die, the cavity, and the multiple conductive bumps. The multiple conductive bumps are exposed from the protection layer.
Claims6
A wafer-level-package device with peripheral side wall protection comprising:
- a die having a top surface, a bottom surface, and a peripheral side wall;
- wherein a cavity is formed on the peripheral side wall of the die and around the die;
- multiple conductive bumps mounted on at least one of the top surface and the bottom surface of the die;
- and
- a protection layer formed by a combination of an upper encapsulant layer and a rear encapsulant layer and covering the top surface, the bottom surface, and the peripheral side wall of the die, the cavity, and the multiple conductive bumps;
- wherein the multiple conductive bumps are exposed from the protection layer;
- wherein top surfaces of the multiple conductive bumps protrude from a top surface of the protection layer;
- wherein the rear encapsulant layer covers the bottom surface of the die.
Dependencies are inferred from the claim text.