Semiconductor device including image sensor and methods of forming the same

A method for forming a semiconductor device, comprising:

• forming a first wafer comprising a first substrate and a first back-end-of-line (BEOL) structure over the first substrate, wherein the first BEOL structure comprises a first metal-insulator-metal (MIM) structure and a thin film transistor, wherein,
• the first MIM structure is formed between a first interconnect and a second interconnect in first metallization layers of the first BEOL structure, and
• the thin film transistor is formed between and connected to the first MIM structure and the first interconnect, wherein a source/drain node of the thin film transistor is in direct contact with the first MIM structure;
• forming a second wafer comprising a second substrate and a second BEOL structure over the second substrate, wherein the second BEOL structure comprises a second MIM structure;
• forming a first hybrid bonding structure, wherein the first hybrid bonding structure is spatially separated from the first MIM structure;
• bonding the first BEOL structure to the second BEOL structure through the first hybrid bonding structure;
• then
• flipping the second wafer to expose a backside of the second substrate;
• then
• forming electrical circuits on the backside of the second substrate;
• then forming a backside BEOL structure on the electrical circuits;
• forming a third wafer comprising a third substrate and a third BEOL structure, wherein the third BEOL structure comprises a third MIM structure;
• forming a second hybrid bonding structure, wherein the second hybrid bonding structure is spatially separated from the third MIM structure;
• and
• bonding the third BEOL structure to the backside BEOL structure of the second wafer through the second hybrid bonding structure.

A method for forming a semiconductor device, comprising:

• bonding a System-on-Chip (SOC) wafer to a front side of a first Application-Specific Integrated Circuit (ASIC) wafer through a hybrid bonding structure, wherein the SOC wafer comprises a first transistor and a first metal-insulator-metal (MIM) structure, the first ASIC wafer comprises a second MIM structure, and the first and second MIM structures are disposed adjacent to a first interface defined by the SOC wafer and the first ASIC wafer;
• forming a second transistor on a backside of the first ASIC wafer after bonding the SOC wafer to the first ASIC wafer;
• forming a backside BEOL structure on the backside of the first ASIC wafer, comprising:
• forming a plurality of inter-metal dielectric (IMD) layers and first interconnects in the IMD layers on the second transistor;
• forming a third MIM structure between two immediately adjacent first interconnects of the first interconnects, wherein the two immediately adjacent first interconnects are disposed in the backside BEOL structure at a level away from the backside of the first ASIC wafer and the hybrid bonding structure;
• and
• connecting a thin film transistor to the third MIM structure, wherein the thin film transistor is formed between and connected to the third MIM structure and one of the two immediately adjacent first interconnects, and a source/drain node of the thin film transistor is in direct contact with the third MIM structure;
• bonding a second ASIC wafer to the backside BEOL structure, wherein the second ASIC wafer comprises a fourth MIM structures disposed adjacent to a second interface defined by the backside BEOL structure and the second ASIC wafer;
• and
• forming micro-lenses over a backside of the SOC wafer.