Technologies for majority gates
AssigneeIntel Corporation
InventorsHai Li, Ian Alexander Young, Dmitri Evgenievich Nikonov, Julien Sebot, Raseong Kim, Chia-Ching Lin, Punyashloka Debashis
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AssigneeIntel Corporation
InventorsHai Li, Ian Alexander Young, Dmitri Evgenievich Nikonov, Julien Sebot, Raseong Kim, Chia-Ching Lin, Punyashloka Debashis
Estimating the term…
Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.
A die comprising a majority gate, the majority gate comprising:
A die comprising a majority gate, the majority gate comprising:
A die comprising:
Dependencies are inferred from the claim text.