Phase-locked loop circuit using hybrid loop calibration scheme and adaptively updated lookup tables and associated clock generating method
AssigneeAiroha Technology Corp.
InventorsHeng-Chih Lin, Shu-Yu Lin
Life of this patent
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Abstract
A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.
Claims20
A phase-locked loop (PLL) circuit comprising:
- a PLL core circuit, arranged to generate an output clock under an open-loop calibration phase and a closed-loop calibration phase;
- at least one lookup table;
- and
- a control circuit, arranged to load PLL parameters that are derived from the at least one lookup table to the PLL core circuit, perform open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and perform closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit, wherein the first part of the PLL parameters that is calibrated by the open-loop calibration comprises a first PLL parameter, the second part of the PLL parameters that is calibrated by the closed-loop calibration comprises a second PLL parameter, the first PLL parameter and the second PLL parameter are different, and the first PLL parameter and the second PLL parameter are applied to different circuits included in the PLL core circuit.
A clock generating method comprising:
- deriving phase-locked loop (PLL) parameters from at least one lookup table;
- loading the PLL parameters to a PLL core circuit, wherein the PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase;
- performing open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit;
- and
- performing closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit, wherein the first part of the PLL parameters that is calibrated by the open-loop calibration comprises a first PLL parameter, the second part of the PLL parameters that is calibrated by the closed-loop calibration comprises a second PLL parameter different, the first PLL parameter and the second PLL parameter are different, and the first PLL parameter and the second PLL parameter are applied to different circuits included in the PLL core circuit.
Dependencies are inferred from the claim text.