Pre-emphasis buffer systems and related methods
AssigneeSemiconductor Components Industries, LLC
InventorsAthar Ali Khan P, Manish Kumar Vishwakarma
Life of this patent
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Abstract
Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.
Claims20
A pre-emphasis signal processing system comprising:
- an output driver comprising:
- a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor are coupled together;
- a regulator voltage input coupled to a source of the pre-emphasis transistor;
- a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver;
- and
- a second resistor coupled between a drain of the steady state transistor and the output of the output driver;
- and
- a pre-emphasis source comprising a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.
A pre-emphasis signal processing system comprising:
- a first output driver comprising:
- a first pre-emphasis transistor coupled with a first steady state transistor, where gates of the first pre-emphasis transistor and the first steady state transistor are coupled together;
- a regulator voltage input coupled to a source of the first pre-emphasis transistor;
- and
- a first signal input coupled with a first buffer chain configured to be coupled to a negative terminal of an input device;
- and
- a first pre-emphasis source comprising a pre-emphasis current source coupled to a first delay transistor, the first delay transistor coupled with an output of the first output driver;
- a second output driver comprising:
- a second pre-emphasis transistor coupled with a second steady state transistor, where gates of the second pre-emphasis transistor and the second steady state transistor are coupled together;
- the regulator voltage input coupled to a source of the second pre-emphasis transistor;
- and
- a second signal input coupled with a second buffer chain configured to be coupled to a positive terminal of the input device;
- and
- a second pre-emphasis source comprising the pre-emphasis current source coupled to a second delay transistor, the second delay transistor coupled with an output of the second output driver.
A method of pre-emphasis signal processing, the method comprising:
- generating rising pre-emphasis in a voltage signal by:
- using a first output driver, turning on a first pre-emphasis transistor, a regulator voltage input coupled with a source of the first pre-emphasis transistor;
- and
- using a first pre-emphasis source, turning on a first delay transistor coupled to a first pre-emphasis current source and to an output of the first output driver;
- increasing an initial voltage of an input signal received by the first output driver using the first pre-emphasis current source and a resistor coupled between a drain of the first pre-emphasis transistor and an output of the first output driver;
- and
- generating falling pre-emphasis in the voltage signal by:
- using a second output driver, turning on a steady state transistor;
- and
- using a second pre-emphasis source, turning off a second delay transistor coupled to the first pre-emphasis current source and with an output of the second output driver;
- and
- decreasing an initial voltage of the input signal received by the second output driver using the first pre-emphasis current source and a resistor coupled between a drain of a second pre-emphasis transistor and an output of the second output driver.
Dependencies are inferred from the claim text.