Reference voltage controlled equalization input data buffer circuit capable of automatically controlling power gain and providing equalization effect

Abstract

A reference voltage controlled equalization input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used for receiving the reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit.

Dependencies are inferred from the claim text.