Three-state programming of memory cells
AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Jeremy M. Hirst, Shanky K. Jain, Richard K. Dodge, William A. Melton
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Abstract
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
Claims11
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
- applying a first voltage pulse having a first polarity to the memory cell;
- determining whether the memory cell snaps back in response to the applied first voltage pulse, wherein a snap back of the memory cell comprises an impedance state of the memory cell changing from a first impedance state to a second impedance state;
- and
- upon determining the memory cell does not snap back in response to the applied first voltage pulse:
- applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity;
- determining whether the memory cell snaps back in response to the applied second voltage pulse;
- applying a plurality of additional voltage pulses to the memory cell upon determining the memory cell does not snap back in response to the applied second voltage pulse, wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein a duration of each respective one of the plurality of additional voltage pulses is shorter than a duration of the first voltage pulse and a duration of the second voltage pulse;
- and
- not applying the plurality of additional voltage pulses to the memory cell upon determining the memory cell snaps back in response to the applied second voltage pulse.
A method of operating memory, comprising:
- programming a memory cell to one of three possible data states by:
- applying a first voltage pulse having a first polarity to the memory cell;
- determining whether the memory cell snaps back in response to the applied first voltage pulse, wherein a snap back of the memory cell comprises an impedance state of the memory cell changing from a first impedance state to a second impedance state;
- and
- upon determining the memory cell does not snap back in response to the applied first voltage pulse:
- applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity;
- determining whether the memory cell snaps back in response to the applied second voltage pulse;
- and
- applying a plurality of additional voltage pulses to the memory cell upon determining the memory cell does not snap back in response to the applied second voltage pulse, wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein a duration of each respective one of the plurality of additional voltage pulses is shorter than a duration of the first voltage pulse and a duration of the second voltage pulse.
Dependencies are inferred from the claim text.