Semiconductor memory with dual quadrature corrected duty cycle clock outputs

A memory system comprising:

• a memory controller configured to transmit a data clock signal and transmit and receive a serial data signal;
• and
• a semiconductor memory device configured to output data stored in a memory cell array as the serial data signal in synchronization with a rising edge of each of a plurality of output clock signals having different phases,
• wherein the semiconductor memory device comprises:
• a data clock buffer configured to receive the data clock signal and generate a pair of differential input signals having two different phases;
• a quadrature error correction circuit (QEC) configured to adjust duty cycles of the pair of differential input signals according to a control code and output a pair of corrected clock signals;
• a first unit delay path circuit configured to generate the pair of corrected clock signals as the plurality of output clock signals;
• a QEC detector configured to detect duty errors of the pair of differential input signals based on the pair of corrected clock signals and generate the control code;
• and
• a second unit delay path circuit configured to generate a plurality of duplicate clock signals that have a same phase and period as the plurality of output clock signals from the pair of corrected clock signals.

A semiconductor memory device comprising:

• a data clock buffer configured to receive a data clock signal from a memory controller and output a pair of differential input signals;
• an output path configured to adjust duty ratios of the pair of differential input signals based on a control code to generate a pair of corrected clock signals and generate four output clock signals having different phases based on the pair of corrected clock signals,
• wherein the output path comprises a first unit delay path circuit configured to receive a pair of delayed clock signals and generate the four output clock signals;
• a rising edge multiplexer configured to serially output data that was input in parallel based on a rising edge of each of the four output clock signals;
• and
• a feedback path configured to generate four duplicate clock signals having different phases based on the pair of corrected clock signals, detect a duty error from the duplicate clock signals, and output the control code corresponding to the duty error that was detected,
• wherein the feedback path comprises a second unit delay path circuit configured to generate the four duplicate clock signals based on the pair of corrected clock signals.